CAMBRIDGE / PROJECT-DEPENDENT DELIVERY
Engineering opportunities, described accurately.
We do not publish placeholder vacancies or unconfirmed employment benefits. For current opportunities, contact the team directly with your location, availability, and technical focus.
Email careersAreas relevant to our work.
Project requirements change. These disciplines describe expertise associated with SVC's published services; they are not claims that a role is currently open.
ASIC and SoC verification
SystemVerilog, UVM, coverage, assertions, integration, and verification planning.
Formal verification
Property development, environment modelling, convergence, proof review, and sign-off evidence.
FPGA and RISC-V
Prototype bring-up, architectural checking, custom extensions, and subsystem verification.
EDA infrastructure
Regression automation, schedulers, CI, observability, reproducibility, and engineering data.
Make the technical fit easy to review.
- 01Your current location, work authorization, and preferred working arrangement.
- 02The verification or design problems you have personally owned.
- 03Tools and languages you have used in production, with the scope of that use.
- 04A concise CV and links to public technical work where available.
- 05Your availability and the type of engagement you are considering.
Ask what is currently open.
Terms, location, assessment, and benefits are confirmed for a specific role in writing. They are not inferred from generic website copy.
careers@siverifconsultants.com